1. Technical Field
The present invention relates generally to memory devices, and more particularly to circuitry that reduces or eliminates data dependent power supply noise when sensing a memory cell.
2. Background Art
For most semiconductor memory devices, including non-volatile memories, a sense amplifier (sense amp) is used to detect or xe2x80x9csensexe2x80x9d the state of a memory cell. The continual scaling of these memory devices results in an ever decreasing amount of current, charge or voltage variation that these sense amplifiers must detect to discern the memory cell state. When a current sense technique is used, the sense amplifier circuit will usually sink or source a different amount of current depending on the xe2x80x9cstatexe2x80x9d of the memory cell being detected. Since typically multiple sense amplifier circuits share a common power supply and are implemented in parallel to concurrently read multiple memory cells, these currents are additive and can lead to a xe2x80x9cdata dependentxe2x80x9d power supply variation or xe2x80x9cspikexe2x80x9d (i.e., current and/or voltage variation). For example, in the extreme case, if all the memory cells to be read in parallel were in the same state, then the collective current sunk or sourced by the power supply upon reading these cells can be rather significant, and may cause a voltage spike as the power supply cannot maintain instantaneous voltage regulation in response to the rapid and significant power (current) demand. Evidently, various combinations of the memory cell states source or sink different amounts of current, and may result in different characteristic voltage variations. These unwanted variations in electrical consumption (i.e., variation in supplied voltage and/or supplied/sunk current) represent noise that can make it difficult for the sense amps to detect the correct data.
Additionally, in systems and devices where such memory devices are used to store secret information (e.g., private keys) for security and privacy (e.g., in a smart card, a mobile telephone, etc.), these data dependent power supply variations may compromise security of the device and the system or network in which the device is used. More specifically, by monitoring the data dependent power supply variations (e.g., the current) while the secure device performs various operations involving secure data reads (e.g., establishing a communication link with another device, performing monetary transactions, etc.), sufficient information may be acquired for determining the xe2x80x9csecurelyxe2x80x9d stored information (e.g., private key).
U.S. Pat. No. 4,932,053 generally addresses this latter security issue associated with data dependent power supply variations by introducing a random current so as to xe2x80x9cmaskxe2x80x9d the current changes and thereby the true value of any data that is being read from memory. Such random currents are introduced by using additional simulation memory cells and a psuedo-random generator for controlling them, thus requiring a significant amount of chip real estate, which real estate may be particularly limited and valuable for various types of secure devices (e.g., smart cards).
U.S. Pat. No. 4,916,333 also addresses this security problem, and discloses a binary logic level detector that has essentially the same electrical consumption regardless of the logic level detected. To provide this essentially data independent consumption, the binary logic level detector consists of two parallel-connected identical read amplifiers that take complementary logic states when they receive the same logic level to be detected, thus essentially doubling the chip real estate required for detecting memory cell logic levels, which is particularly not well suited when using high sensitivity sense amplifiers that employ numerous transistors.
It may be appreciated, therefore, that there remains a need for further advancements and improvements in reducing, eliminating, or minimizing power supply variations when sensing the state of a memory cell, and particularly for circuitry that provides reduced data dependent power supply variations without requiring significant chip real estate, while being well suited for implementation with conventional sense amplifier designs.
The present invention provides such advancements and overcomes the above mentioned problems and other limitations of the background and prior art, by providing a logic level detection circuit that includes a sense amplifier and a consumption equilibration circuit that is topologically distinct from the sense amplifier and that reduces and/or eliminates data dependent electrical consumption by having a data dependent electrical consumption that compensates the data dependent electrical consumption of the sense amplifier.
In accordance with an aspect of the present invention, a logic level detection circuit includes a sense amplifier that has a first current consumption when sensing a first logic level, and a second current consumption when sensing a second logic level, the first and second current consumptions being different by a first amount. The logic level detection circuit also includes a consumption equilibration circuit that has a transistor configuration distinct from the sense amplifier and is supplied by a power source that also supplies the sense amplifier. The consumption equilibration circuit has a third current consumption when the sense amplifier senses the first logic level, and a fourth current consumption when the sense amplifier senses the second logic level. The magnitude of the difference between (i) the sum of the first and third current consumptions and (ii) the sum of the second and fourth consumptions is less than the magnitude of the first amount, thus reducing logic level (data or state) dependent electrical consumption.
In accordance with a further aspect of the present invention, the difference is reduced such that the combined current consumption of the sense amplifier and the consumption equilibration circuit when the sense amplifier senses the first and second logic levels is substantially independent of the logic level detected.
In accordance with another aspect of the present invention, the sense amplifier is implemented as a current-sensing sense amplifier, and the consumption equilibration circuit is implemented as a selectively enabled current source. Additionally, this selectively enabled current source may be responsive to a signal generated by the current-sensing sense amplifier when this sense amplifier senses a logic level. The consumption equilibration circuit may be implemented with a number of transistors that is at least three times less than the number of transistors used for implementing the sense amplifier.
In accordance with yet another aspect of the present invention, the logic level detection circuit is integrated with a memory cell array on a common semiconductor substrate, which may include integration of other circuitry, such as a microprocessor, input/output and communications circuitry. Such a logic level detection circuit integrated with at least a memory cell array may be included in an integrated circuit implemented as a smart card.